Proper operation of high-speed CMOS integrated circuits generally requires accurate transition edge alignment between certain internal digital signals. For example, a typical CMOS divider circuit may receive as inputs a high-speed clock signal and a relatively lower speed logic signal such as a return-to-one or return-to-zero set/reset signal. The timing relationship between the clock signal transition edge and the logic signal transition edge must be maintained properly in order to ensure reliable operation of the divider circuit to which these signals may be applied. In many applications, the high-speed clock signal and the logic signal may be applied to a latch in which the clock signal transition edge is used to latch a particular logic state of the logic signal. Failure to provide the proper transition edge alignment at the input of the latch can lead to metastability within the latch or subsequent circuitry.
A conventional technique for providing edge alignment between such digital signals involves the use of double sampling. However, edge alignment circuits based on double sampling are unduly complex and therefore decrease the reliability and increase the cost and chip area of the corresponding integrated circuit. Furthermore, edge alignment circuits based on double sampling are generally susceptible to metastability as well.
It is therefore apparent that a need exists for an improved transition edge alignment technique which is simple to implement, resistant to metastability and suitable for use in many practical high-speed integrated circuit applications.